In conventional semiconductor devices, in order to effectively suppress variations in etching and proximity effects, as many gate-layer dummy patterns as possible were formed in the chip (see patent documents 1 and 2). In the invention disclosed in patent document 1, in order to suppress variations in etching, dummy patterns were formed between adjacent gates. In the invention disclosed in patent document 2, in order to prevent proximity effects when forming the gate pattern by photolithography, a dummy gate (dummy pattern) was located in a dummy element area that was formed in an element isolation area. This kind of dummy pattern was located on the semiconductor substrate, or above a well having different electric potential than the wiring (a well with identical conductivity type as the substrate).
However, in conventional semiconductor devices, as the film thickness of the insulating film between layers becomes thicker, the aspect ratio of the contact holes and via holes becomes larger and it becomes difficult to put the conductor inside the holes; and as the holes become deeper, there is a possibility that the contact resistance will increase, so the film thickness of the insulating layers between layers is becoming thinner.
[Patent Document 1]
U.S. Pat. No. 5,899,706
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2001-168205A